|
| |
Neil Paton
| 1 |
6,072,568 |
|
Thermal barrier coating stress measurement |
| 2 |
5,679,270 |
|
Method for removing ceramic material from castings using caustic medium
with oxygen getter |
| 3 |
4,761,187 |
|
Method of improving stress corrosion resistance of alloys |
| 4 |
4,716,270 |
|
Non-contact scribing process for organic maskants on metals or alloys
thereof |
| 5 |
4,469,757 |
|
Structural metal matrix composite and method for making same |
| 6 |
4,358,324 |
|
Method of imparting a fine grain structure to aluminum alloys having
precipitating constituents |
| 7 |
4,299,626 |
|
Titanium base alloy for superplastic forming |
| 8 |
4,233,829 |
|
Apparatus for superplastic forming |
| 9 |
4,229,216 |
|
Titanium base alloy |
| 10 |
4,222,797 |
|
Method of imparting a fine grain structure to aluminum alloys having
precipitating constituents |
| 11 |
4,181,000 |
|
Method for superplastic forming |
| 12 |
4,092,181 |
|
Method of imparting a fine grain structure to aluminum alloys having
precipitating constituents |
Eric Paton
| 1 |
6,924,182 |
|
Strained silicon MOSFET having reduced leakage and method of its
formation |
| 2 |
6,921,709 |
|
Front side seal to prevent germanium outgassing |
| 3 |
6,905,923 |
|
Offset spacer process for forming N-type transistors |
| 4 |
6,902,966 |
|
Low-temperature post-dopant activation process |
| 5 |
6,878,592 |
|
Selective epitaxy to improve silicidation |
| 6 |
6,878,559 |
|
Measurement of lateral diffusion of diffused layers |
| 7 |
6,873,051 |
|
Nickel silicide with reduced interface roughness |
| 8 |
6,867,428 |
|
Strained silicon NMOS having silicon source/drain extensions and method
for its fabrication |
| 9 |
6,867,080 |
|
Polysilicon tilting to prevent geometry effects during laser thermal
annealing |
| 10 |
6,858,503 |
|
Depletion to avoid cross contamination |
| 11 |
6,825,115 |
|
Post silicide laser thermal annealing to avoid dopant deactivation
|
| 12 |
6,812,550 |
|
Wafer pattern variation of integrated circuit fabrication |
| 13 |
6,812,106 |
|
Reduced dopant deactivation of source/drain extensions using laser
thermal annealing |
| 14 |
6,811,448 |
|
Pre-cleaning for silicidation in an SMOS process |
| 15 |
6,806,172 |
|
Physical vapor deposition of nickel |
| 16 |
6,797,614 |
|
Nickel alloy for SMOS process silicidation |
| 17 |
6,787,864 |
|
Mosfets incorporating nickel germanosilicided gate and methods for their
formation |
| 18 |
6,784,506 |
|
Silicide process using high K-dielectrics |
| 19 |
6,780,789 |
|
Laser thermal oxidation to form ultra-thin gate oxide |
| 20 |
6,773,978 |
|
Methods for improved metal gate fabrication |
| 21 |
6,764,912 |
|
Passivation of nitride spacer |
| 22 |
6,746,944 |
|
Low nisi/si interface contact resistance with preamorphizing and laser
thermal annealing |
| 23 |
6,743,689 |
|
Method of fabrication SOI devices with accurately defined
monocrystalline source/drain extensions |
| 24 |
6,730,576 |
|
Method of forming a thick strained silicon layer and semiconductor
structures incorporating a thick strained silicon layer |
| 25 |
6,727,176 |
|
Method of forming reliable Cu interconnects |
| 26 |
6,703,648 |
|
Strained silicon PMOS having silicon germanium source/drain extensions
and method for its fabrication |
| 27 |
6,703,277 |
|
Reducing agent for high-K gate dielectric parasitic interfacial layer
|
| 28 |
6,689,688 |
|
Method and device using silicide contacts for semiconductor processing
|
| 29 |
6,682,973 |
|
Formation of well-controlled thin SiO, SiN, SiON layer for multilayer
high-K dielectric applications |
| 30 |
6,680,250 |
|
Formation of deep amorphous region to separate junction from
end-of-range defects |
| 31 |
6,656,749 |
|
In-situ monitoring during laser thermal annealing |
| 32 |
6,646,307 |
|
MOSFET having a double gate |
| 33 |
6,638,861 |
|
Method of eliminating voids in W plugs |
| 34 |
6,632,729 |
|
Laser thermal annealing of high-k gate oxide layers |
| 35 |
6,605,513 |
|
Method of forming nickel silicide using a one-step rapid thermal anneal
process and backend processing |
| 36 |
6,602,781 |
|
Metal silicide gate transistors |
| 37 |
6,562,718 |
|
Process for forming fully silicided gates |
| 38 |
6,559,051 |
|
Electroless deposition of dielectric precursor materials for use in
in-laid gate MOS transistors |
| 39 |
6,555,439 |
|
Partial recrystallization of source/drain region before laser thermal
annealing |
| 40 |
6,551,888 |
|
Tuning absorption levels during laser thermal annealing |
| 42 |
6,536,370 |
|
Elapsed time indicator for controlled environments and method of use
|
| 43 |
6,514,859 |
|
Method of salicide formation with a double gate silicide |
| 44 |
6,475,874 |
|
Damascene NiSi metal gate high-k transistor |
| 45 |
6,465,334 |
|
Enhanced electroless deposition of dielectric precursor materials for
use in in-laid gate MOS transistors |
| 46 |
6,465,309 |
|
Silicide gate transistors |
| 47 |
6,458,679 |
|
Method of making silicide stop layer in a damascene semiconductor
structure |
| 48 |
6,432,805 |
|
Co-deposition of nitrogen and metal for metal silicide formation
|
| 49 |
6,399,467 |
|
Method of salicide formation |
| 50 |
6,387,786 |
|
Method of salicide formation by siliciding a gate area prior to
siliciding a source and drain area |
| 51 |
6,368,950 |
|
Silicide gate transistors |
| 52 |
6,342,414 |
|
Damascene NiSi metal gate high-k transistor |
| 53 |
6,300,203 |
|
Electrolytic deposition of dielectric precursor materials for use in
in-laid gate MOS transistors |
| 54 |
6,297,159 |
|
Method and apparatus for chemical polishing using field responsive
materials |
| 55 |
6,297,107 |
|
High dielectric constant materials as gate dielectrics |
| 56 |
6,048,790 |
|
Metalorganic decomposition deposition of thin conductive films on
integrated circuits using reducing ambient |
|